exceptions and interrupts
      transfer of control is via a vector held in a table at VECTORBASE
      different causes routed through different vectors, e.g.,
        interrupt 1-7
        trap 0-15
        illegal instruction
        divide by zero
      saves status register(SR) and PC (and optional data) on stack
      interrupts may be held off by processor priority (noted in SR)
      SystemBit set to 1, TraceBit set to 0
      RTE restores SR and PC
    

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CSci281/0226.html was last edited by Randolph Bentson, on 2007/02/26T13:21:45-08:00