Our textbook has described the internals of SRC in terms of basic logic elements. These descriptions are broken into components / sub-circuits as follows.

• Fig 4.4 - The Register File
• Fig 4.5 - Extracting c1,c2,OP from IR
• Fig 4.6 - Memory Interface
• Fig 4.7 - ALU and associated registers
• Fig 4.8 - one bit of ALU
• Fig 4.9 - Shift Counter
• Fig 4.10 - computing CON
• Fig 4.14 - Step Generator / branching
• Fig 4.15 - Clocking Logic
• Control Signal encoder

These circuits can be simulated with a tool such as Logisim. There are local downloads available for Windows, Mac OS, and general (Linux), as well as a copy of many of the author's web pages.

I've built the circuit for the Memory Interface which you can download and examine. When doing so, I found the need to build a trivial helper device which you can also download and examine.

If you want to explore further, others have written descriptions of a number of common MSI chips in the 7400 series, and have implemented some simple counters. The former used the interactive Logisim to build the devices, while the latter implemented them as Java code to be used inside Logisim. Use Project > Load Library > Logisim Library or Project > Load Library > JAR Library to load them.

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CSci281/0403.html was last edited by Randolph Bentson, on 2007/04/03T13:43:34-07:00